configurable wire from one module to another module in verilog

[tariq786]

Hi,

I want to know if there is a way in verilog to configure a wire from one module to another module such that during simulation, it exists as a regular wire for some simulation time and then as no wire for remaining simulation time. Here is what i mean

 

[dave_59]

You ask a lot of strange questions. How is the different from inserting a bufif0 primitive in the path if wire y?