Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

configurable wire from one module to another module in verilog

Status
Not open for further replies.

tariq786

Advanced Member level 2
Joined
Feb 24, 2004
Messages
562
Helped
67
Reputation
134
Reaction score
53
Trophy points
1,308
Location
USA
Activity points
3,048
Hi,

I want to know if there is a way in verilog to configure a wire from one module to another module such that during simulation, it exists as a regular wire for some simulation time and then as no wire for remaining simulation time. Here is what i mean


 

Attachments

  • configurable_wire_verilog.jpg
    configurable_wire_verilog.jpg
    41.3 KB · Views: 129

You ask a lot of strange questions. How is the different from inserting a bufif0 primitive in the path if wire y?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top