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coneverting into VHDL

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nur 'afiqah jaini

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can somebody help me translate it into VHDL code?
i was doing a project using DE2 board and VHDL languange..
but i only found this coding at fpga4fun..
can somebody help me?

Code:
module music(clk, speaker);
input clk;
output speaker;

reg [27:0] tone;
always @(posedge clk) tone <= tone+1;

wire [5:0] fullnote = tone[27:22];

wire [2:0] octave;
wire [3:0] note;
divide_by12 divby12(.numer(fullnote[5:0]), .quotient(octave), .remain(note));

reg [8:0] clkdivider;
always @(note)
case(note)
  0: clkdivider = 512-1; // A 
  1: clkdivider = 483-1; // A#/Bb
  2: clkdivider = 456-1; // B 
  3: clkdivider = 431-1; // C 
  4: clkdivider = 406-1; // C#/Db
  5: clkdivider = 384-1; // D 
  6: clkdivider = 362-1; // D#/Eb
  7: clkdivider = 342-1; // E 
  8: clkdivider = 323-1; // F 
  9: clkdivider = 304-1; // F#/Gb
  10: clkdivider = 287-1; // G 
  11: clkdivider = 271-1; // G#/Ab
  12: clkdivider = 0; // should never happen
  13: clkdivider = 0; // should never happen
  14: clkdivider = 0; // should never happen
  15: clkdivider = 0; // should never happen
endcase

reg [8:0] counter_note;
always @(posedge clk) if(counter_note==0) counter_note <= clkdivider; else counter_note <= counter_note-1;

reg [7:0] counter_octave;
always @(posedge clk)
if(counter_note==0)
begin
 if(counter_octave==0)
  counter_octave <= (octave==0?255:octave==1?127:octave==2?63:octave==3?31:octave==4?15:7);
 else
  counter_octave <= counter_octave-1;
end

reg speaker;
lways @(posedge clk) if(counter_note==0 && counter_octave==0 && tone[30]==0 && fullnote!=0) speaker <= ~speaker;
endmodule

module divide_by12(numer, quotient, remain);
input [5:0] numer;
output [2:0] quotient;
output [3:0] remain;

reg [2:0] quotient;
reg [3:0] remain_bit3_bit2;

assign remain = {remain_bit3_bit2, numer[1:0]}; // the first 2 bits are copied through

always @(numer[5:2]) // and just do a divide by "3" on the remaining bits
case(numer[5:2])
  0: begin quotient = 0; remain_bit3_bit2 = 0; end
  1: begin quotient = 0; remain_bit3_bit2 = 1; end
  2: begin quotient = 0; remain_bit3_bit2 = 2; end
  3: begin quotient = 1; remain_bit3_bit2 = 0; end
  4: begin quotient = 1; remain_bit3_bit2 = 1; end
  5: begin quotient = 1; remain_bit3_bit2 = 2; end
  6: begin quotient = 2; remain_bit3_bit2 = 0; end
  7: begin quotient = 2; remain_bit3_bit2 = 1; end
  8: begin quotient = 2; remain_bit3_bit2 = 2; end
  9: begin quotient = 3; remain_bit3_bit2 = 0; end
  10: begin quotient = 3; remain_bit3_bit2 = 1; end
  11: begin quotient = 3; remain_bit3_bit2 = 2; end
  12: begin quotient = 4; remain_bit3_bit2 = 0; end
  13: begin quotient = 4; remain_bit3_bit2 = 1; end
  14: begin quotient = 4; remain_bit3_bit2 = 2; end
  15: begin quotient = 5; remain_bit3_bit2 = 0; end
endcase
endmodule

reg [30:0] tone;
always @(posedge clk) tone <= tone+1;

wire [7:0] fullnote;
music_rom rom(.inclock(clk), .outclock(clk), .address(tone[29:22]), .q(fullnote));

- - - Updated - - -

this is the simple one
can somebody help me to translate it?
Code:
module music(clk, speaker);
input clk;
output speaker;

reg [14:0] counter;
always @(posedge clk) if(counter==28408) counter <= 0; else counter <= counter+1;

reg speaker;
always @(posedge clk) if(counter==28408) speaker <= ~speaker;
endmodule
 
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I think you can find a VHDL equivalent of this code in some files that come along with the DE2 board. Try the Altera website. There's a code which connects the mic to the speaker. One of my friends used this code for some adaptive filtering work.
 

I think Xilinx used to have a verilog->VHDL converter. check their website.
 

I'm not aware of a Xilinx converter tool. ISE is supporting mixed language, I think.

You can refer to this previous thread for some thoughts about Verilog to VHDL conversion (or vice-versa) and available tools:
https://www.edaboard.com/threads/115689/

The above (almost trivial) code can be easily translated line by line, I think.
 

"used to" is the operative phrase. It was a utility that was included with ISE (or whatever its predecessor was). I used it once, but that was a long time ago. It must be floating around the web somewhere...
 

O.K., this might be, in this case the tool shares the destiny of StateCad, which has been obsoleted in ISE11.

But I still wonder why the tool has never been mentioned in discussions about converters? If it has been in a previous Xilinx distribution, some people shoudl know it. Although not me, because I never used Xilinx for real projects.
 

I think it was some tcl tool that is embedded in core generator that was used to create the VHDL version of a parameterized core from a verilog description. barry probably used the tcl script directly.

I have a vague recollection of asking the FAE about this as I needed a mixed license on a VHDL only project to support the core generator output that was only in verilog. I think the answer was all the cores are in verilog and the tool converts it to VHDL if requested by the user.

-alan
 
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    FvM

    Points: 2
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"used to" is the operative phrase. It was a utility that was included with ISE (or whatever its predecessor was). I used it once, but that was a long time ago. It must be floating around the web somewhere...

Are you sure you're not thinking of an AHDL -> VHDL/Verilog converter? Xilinx still provide this (the XPort utility).
 

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