Concatenation problem in port map in vhdl

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moonshine8995

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Concatination problem in port map in vhdl

i want to port map
Code: 
out_x=> mid
out is 32 bit std_logic_vector and mid is 16 bit std_logic_vector.
how should i do this?
i change it to this
Code: 
out  => (x"0000" &mid)
but i see this error
Code: 
Formal "out_x" of mode OUT cannot be associated with an expression.
thanks.
 

Re: concatination problem in port map in vhdl

Out(15 downtown 0) => mid;
 

Re: concatination problem in port map in vhdl

the out and mid size shouldn't be changed!
 

Re: concatination problem in port map in vhdl

moonshine8995 said:
the out and mid size shouldn't be changed!
Click to expand...

I dont get what you're talking about, I didnt change any sizes, I just assigned the 16 LSBs of out to mid. You can assign the 16 MSbs to whatever you want:

Code: 
out(31 downto 16) => x"0000",
Out(15 downto 0) => mid,
 

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