[SOLVED] concatenation in verilog synthesis

[Mina Magdy]

was concatenation in verilog synthesis or not synthisis and if it is not how can i replace it?
thank you

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another question
was function synthesis ?
if yes why i cant see what inside it as number of regs,ram,rom ....etc

 

[FvM]

Two points.
- concatenation can be used in synthesizable Verilog without restriction
- strictly spoken, it doesn't involve any logic resources, it's just connecting existing wires. You can say, there's nothing to synthesize at all.

 

[Mina Magdy]

thank you
i dont undrstand point two
do you mean that i cant make logic in side the function i mean binary adder function and binary subtractor and became synthesis?

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function [7:0] subadd;
input [7:0] A_b;
input [7:0] B_b;
input ctrl_b;
reg [7:0] C_b;

reg [6:0] A_b_1;
reg [6:0] B_b_1;
reg [6:0] C_b_1;
reg A_b_2;
reg B_b_2;
reg C_b_2;
begin
A_b_2=A_b[7];
B_b_2=B_b[7];

if(ctrl_b==1)
begin


if((A_b_2==0)&&(B_b_2==0))
begin
C_b_1=A_b_1+B_b_1;
C_b_2=0;
end
else if((A_b_2==1)&&(B_b_2==1))
begin
C_b_1=A_b_1+B_b_1;
C_b_2=1;
end
else if((A_b_2==0)&&(B_b_2==1))
begin
if(A_b_1>=B_b_1)
begin
C_b_1=A_b_1-B_b_1;
C_b_2=0;
end
else
begin
C_b_1=B_b_1-A_b_1;
C_b_2=1;
end
end
else if((A_b_2==1)&&(B_b_2==0))
begin
if(A_b_1>=B_b_1)
begin
C_b_1=A_b_1-B_b_1;
C_b_2=1;
end
else
begin
C_b_1=B_b_1-A_b_1;
C_b_2=0;
end
end
C_b={C_b_2,C_b_1};
end


else
begin
if((A_b_2==0)&&(B_b_2==1))
begin
C_b_1=A_b_1+B_b_1;
C_b_2=0;
end
else if((A_b_2==1)&&(B_b_2==0))
begin
C_b_1=A_b_1+B_b_1;
C_b_2=1;
end
else if((A_b_2==0)&&(B_b_2==0))
begin
if(A_b_1>=B_b_1)
begin
C_b_1=A_b_1-B_b_1;
C_b_2=0;
end
else
begin
C_b_1=B_b_1-A_b_1;
C_b_2=1;
end
end
else if((A_b_2==1)&&(B_b_2==1))
begin
if(A_b_1>=B_b_1)
begin
C_b_1=A_b_1-B_b_1;
C_b_2=1;
end
else
begin
C_b_1=B_b_1-A_b_1;
C_b_2=0;
end
end
C_b={C_b_2,C_b_1};
end
end
subadd = C_b;
end
endfunction
can this be synthesised

 

[mrflibble]

No I don't think he meant that. Because that's not what he said.

What he said was that you can do concatenation on any signal. If it's a signal just in a simulator, you can concatenate it. If it's a signal in real actual hardware (coming out of an adder for example), you can concatenate it. If it's a magic signal, you can concatenate it.

concatenate really is nothing more than: bundle of wires C = "bundles of wires A" in parallel with "bundle of wires B"

For example:

wide_bus = {MSB_part , LSB_part}

MSB_part and LSB_part are both 8 bits. And wide_bus (the concatenation result) is 16-bits.

Short version to your OP: Yes you can use concatenation in synthesis.