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comunication problems

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amitaiwe

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Hi all,
As part of a circuit I'm using transmitting data from a uC (PIC16f877) to a
Bluetooth module (RN42SM) via a UART protocol. The BT is supposed to act
as a pipe and transmit the data to a PC's terminal.

For the sake of making sure that the communication works properly there's
a sequence of 5 4 3 2 1 data transmitted before the main loop of the uC operation.
The main data which is transmitted is 16 data registers which are been sent every
operation cycle. Their address is from 0x35 to 0x44.
The values of these registers can't be known in advance and therefor can't be
verified as true. In order to check that these registers are transmitted as
their true value and are not Disrupted I have simulated values to these registers
from 1 to 16.
The values received in the terminal were:
05 04 03 02 01 (as expected)
FF FE FD FC FB ... FF FE FD FC ....
i.e. a mirror type from -1 to -16.
Trying to do the same using the mplab debug simulator showed good results-
The 35-44 registers had their true values and the transmitting values were correct too.
(see code "to_transmit")

I don't manage to understand why the demo values are transmitted with no errors and
the rest of the data is disturbed?
Can someone help me with solving the problem?
I am attaching the code which I Adjusted for the simulated data values.
Thanks, Amitai

the assembly code:
Code:
LIST	P=PIC16F877
    	
include	<P16f877.inc>
org		0x00

	__CONFIG _LVP_OFF &_WDT_OFF &_PWRTE_OFF &_CP_OFF & _HS_OSC	

reset:
nop
goto	start
org		0x20

start:

; configuration
;-----------------------------------

; used_registers:
	cnt1			EQU H'0021'  		; first counter 
	del1			EQU H'0022'  		; for delay
	del2			EQU H'0023'  		; for delay
	to_transmit		EQU H'0025'  		; data transmitted register
	led1			EQU H'0026'  		; for led delay
	demo_tr			EQU H'0027'  		; demo transmit
	cnt2			EQU H'0028'  		; second counter 
	FE_change		EQU H'0029'  		; for not transmitting FF
	sim_numbers		EQU H'0030'  		; for usage of demo values
	; 35-45		timers value

	
	banksel		ADCON1
	movlw		0x07				; ADC PINS configured as a digital I/O									
	movwf		ADCON1

;UART ******************************
	banksel		TRISC
	bsf	 	 	TRISC, 6 
	bsf		 	TRISC, 7	
	
	banksel  	TXSTA
	movlw    	0xA7        		; master, transmit EN, Async mode, Transmit Shift Register empty, BRGH =1
	movwf    	TXSTA	       		; Baud Rate = Fosc/(16(SPBRG+1)) , BRGH (baud rate) ignored in sync
	
	banksel		SPBRG
	movlw	 	0x08		   		; = d"3" which corresponds to 125Kbps with 8MHz clock
	movwf	 	SPBRG
	
	banksel  	RCSTA
	movlw    	0x80		  		; enable UART	
	movwf    	RCSTA
; end configuration --------------------------------------


;*****************************************
;************ MAIN PROGRAM ***************
;*****************************************

main:
	
;counters initialize ***************************
	movlw		0x07
	movwf		cnt1
	movlw		0x08
	movwf		cnt2
	
;transmit check  ********************
    movlw		0x05					; demo check
	movwf		demo_tr
	tra:
	CALL		DELAY
	movf		demo_tr, w
	movwf		to_transmit 
	CALL 		transmitting_data
	decfsz		demo_tr
	goto		tra   	
	
main_loop:
	movlw		0x35
	movwf		FSR	
	movlw		0x08
	movwf		cnt2
	movlw		0x01
	movwf		sim_numbers

save_loop:
	movf		sim_numbers,w
	movwf		INDF
	incf		FSR
	movf		sim_numbers,w
	movwf		INDF
	incf		FSR
	incf		sim_numbers
	
;counter increment
	decf		cnt1,f
	decfsz		cnt2
	goto		save_loop
	movlw		0x07
	movwf		cnt1
	
;transmitting data *****************
	movlw		0x35
	movwf		FSR
	movlw		0x10
	movwf		cnt2
	
	trans_loop:
	CALL		DELAY
	movf		INDF,w
	movwf		to_transmit							
	CALL 		transmitting_data
	incf		FSR
	decfsz		cnt2
	goto		trans_loop
	goto		main_loop
				
				
;******** END MAIN LOOP ********************		

transmitting_data:	
	banksel		TXREG
	movwf   	TXREG					    	; writing to TXREG clears TXIF
    trans_wait2:
	btfss		PIR1, TXIF						; wait for the frame to be transmitted
	goto		trans_wait2
	CALL		DELAY
	return
	
DELAY:
	movlw		0x40
	movwf		del1
	movlw		0x40
	movwf		del2
	
	loopa:
	decfsz		del1, f
	goto		loopa
	loopb:
	decfsz		del2, f
	goto		loopb
	return
		
end
 

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