Computer arithmetic units

[Rocky1943]

Hi, everyone,

do you usually use arithmetic units(+ - * /) in your designs?
because there are many kind of algorithms for these arithmetic units,
I haven't find many IP for these funtions, many be these units are mainly used in
processors.
because I am doing some research in Computer arithmetic, I want to make all IPs for these units, but I don't know it is necessary or not.

Thanks.

regards

Rocky

 

[echo47]

With modern FPGAs, you can use integer addition, subtraction, and multiplication operators directly in your HDL, and you should get good optimized results from the synthesis tools. However, division is not supported very well in most tools, so you may need to design your own divider or use an IP core (it may be provided with the software tools).

 

[Rocky1943]

Thanks, echo,
and I am still a little bit confused about my research.
because I am doing computer arithmetic research, and try to figure out some efficient elementary units. I saw my contemparts in our lab implement these designs in fpga, so I think it would not reveal the true performance of my design.
because so far as I know, the performance of my design in fpga would have a great deal relationship with the architecture of fpga and my code style as well , which need to comply with the feture of fpga.
So what's your opinion of my work?
is this meaningful?

Thanks
rocky

 

[echo47]

Modern FPGA's contain special dedicated logic (such as fast carry chain) that speeds up arithmetic operations. The synthesis software automatically uses those features as it compiles HDL arithmetic expressions. If you try to design your own arithmetic logic without taking advantage of those special features, your logic will probably be bulky and slow.

Xilinx's FPGA tools let you directly access those special features as library primitives, but they are tedious to use. You may be able to build arithmetic that's a little better than ordinary synthesized HDL, but the improvement may not be worth the effort for most users.

Yes, the FPGA's special features do vary between different FPGA families. You may need to carefully adjust your code for each FPGA family.

 

[FvM]

I think, a lot of projects has been dealing with the topic, I often stumble over it at the internet. Thus there may be a lack of originality. But I'm just a user of numerical mathematics and don't know about possible unresolved problems in this field.

 

[Rocky1943]

ye, Thanks for your guys,

I will get familiar with various algorithms of these units, and figure out these ip.
IF POSSIble, I will share these codes with you.

if you need these algorithms or have other Qs, you can contact with me.


Email: turkey1943at gmail.com

 

[echo47]

If you discover better methods than the HDL synthesis tools provided by the FPGA manufacturer, then please tell the manufacturer what you've done so they can improve their tools for everyone's benefit. I've given Xilinx various suggestions for improving XST optimization, and they have implemented some of them.

 

[Rocky1943]

Hi, Echo,

It seems that u r quite familiar with FPGA optimization and synthesis,
It's quite a good and interesting idea for doing this.
now, I have several Questions for this.

So right now I don't know how to start, can you briefly introduce that to me?
because you have some experience in this part.
before I can get a better results, I need to get familiar with fpga achitecture? and know how synthesis tools get the results?

I am very appreciated with your suggestion, because I found that the performance of the computer arithmetic units seems not quite good in Fpga. So I may do some research in how to implement these efficient units in FPGA and get the best results.

regards

 

[echo47]

I suggest first investigating why your currently synthesized results are not as good as you expected. Perhaps your expectations are too high, or perhaps the synthesis tool isn't efficiently optimizing your HDL for some reason.

You haven't said which FPGA and synthesizer tool you are using, but your synthesizer user manual probably explains how to write HDL to help the synthesizer produce good optimized results. For example, the Xilinx ISE 10.1i "XST User Guide" has two relevant chapters, "XST HDL Coding Techniques" and "XST FPGA Optimization".

If you wish to try configuring you FPGA at low level (to directly access small features such as LUTs, flops, carry chains, muxes, etc.), you'll need to study your FPGA user manual, the synthesis library manual, and maybe some application notes to learn all the gory details. That's for Xilinx, I'm not sure about others.

 

[Rocky1943]

Thanks