What do u mean by computational time? I think whatever you are referring to will be available in the FPGA specific datasheet..
Combinatorial logic has propagation delay, is that what you mean?
If so you could place the logic between two registers and find the maximum clock rate at which the circuit meets timing, which will be the sum of the logic and register propagation delays.
This is highly routing dependent obviously, and superficially the same logic can have widely different propagation delays depending on how the fitter has placed it (Which, if you have fully constrained the timing does not matter in practise).
The registers have the usual setup and hold times and a maximum clock rate (which will be given in the datasheet for the part).
Highest thruput is when you pipeline and register often enough to ensure the clock is the limiting factor not the internal setup and hold timing, which usually requires that the amount of combinatorial logic between registers be kept fairly small (Carry chains in simple minded ALUs are often the acid test here).
Lowest latency often comes from sacrificing clock speed to minimising the number of pipeline stages.
FPGAs are NOT CPUs, do not try to treat a HDL as programming, treat it as logic design.