component in process

[h.m]

if we can't use component statements in process,so we can't have them(component statements) in a for loop,am i right?
if yes,what should i do?i have some component statements that must be repeated many times :?: :!:

 

[aruipksni]

if we can't use component statements in process,so we can't have them(component statements) in a for loop,am i right?
if yes,what should i do?i have some component statements that must be repeated many times :?: :!:

you will need to use them in a "generate" clause

something like :

xi :for i in x'range generate

x : entity work. foo (x => y);

end generate xi;

 

[h.m]

sorry,my question was not complete,i want to have component statements and some other things with each other in a loop but it can't be possible, generate is just for components...
k(4)<=k(4+6*j);
k(5)<=k(5+6*j);
k(6)<=k(6+6*j);
--component statements
fa1:multiply port map (x(1),k(1),f(1));
fa2:faadd port map (x(2),k(2),f(2));
fa3: faadd port map (x(3),k(3),f(3));
fa4:multiply port map (x(4),k(4),f(4));
f(5)<=f(1) xor f(3);
i want to have these lines in a loop
tnx alot fo your help

 

[aruipksni]

sorry,my question was not complete,i want to have component statements and some other things with each other in a loop but it can't be possible, generate is just for components...
k(4)<=k(4+6*j);
k(5)<=k(5+6*j);
k(6)<=k(6+6*j);
--component statements
fa1:multiply port map (x(1),k(1),f(1));
fa2:faadd port map (x(2),k(2),f(2));
fa3: faadd port map (x(3),k(3),f(3));
fa4:multiply port map (x(4),k(4),f(4));
f(5)<=f(1) xor f(3);
i want to have these lines in a loop
tnx alot fo your help

no problem to assign segnals with generate.
however, it is not clear what you want to achieve in puting those assigment in a loop.

 

[h.m]

thank u thank u,my mistake was another thing,in a for loop,it wasn't error to write 0 downto 6 or to 6; but in a generate one,we should write( 0 downto 7 ) or (7 to 0),and other cases are wrong!am i right?
it is my first project,tnx alot

- - - Updated - - -

if u can have a value as a signal and also variable,which of them should be chosen? ofcourse signal will cause more warnings!

 

[aruipksni]

thank u thank u,my mistake was another thing,in a for loop,it wasn't error to write 0 downto 6 or to 6; but in a generate one,we should write( 0 downto 7 ) or (7 to 0),and other cases are wrong!am i right?
it is my first project,tnx alot

- - - Updated - - -

if u can have a value as a signal and also variable,which of them should be chosen? ofcourse signal will cause more warnings!

you should write 7 downto 0 -- 7 is greater then 0 or
0 to 7 -- again 7 is greater then 0

 

[TrickyDicky]

0 downto 7 produces a null range, as does 7 to 0.
You should always pick signals until you learn how VHDL works. Variables can be confusing when you dont understand them, and what logic they will produces. So the easy advice is always stick with signals.

 

[h.m]

i should do this project to pass this course,and i should program it on a real fpga,so if it's possible to u,please tell me more about signals and variables.

 

[bking]

The most important things to remember about variables are:

They can only appear inside of a process
The assignment operator is := , not <=
The value gets updated immediatly upon a new assignment whereas a signal only gets updated when the process suspends.

The big difference is that last one. If you don't understand the differences in how variables and signals change you are looking at potential errors in your design. As Tricky said, avoid variables unless you really understand them and have a need for them. In most cases you probably do not have a need.

 

[h.m]

tnx for you,re complete answer:i knew them,and i,m in a situation that both of them will work correctly,and signal one has more warning so which of them is better?again thank you