power consumption in static and dynamic logics
The Complementary CMOS circuit design falls under two categories:
1. Static
2. Dynamic
1.Static CMOS
In Static CMOS design, at every point in time, each gate output is connected to either Vdd or Vss via a low-resistance path. Also, the outputs of the gate assume at all times the value of the Boolean function implemented by the circuit.
A Static CMOS gate is a combination of two networks - the pull-up netowrk (PUN) and the pull-down network (PDN). The function of the PDN is to provide a connection between the output and Vdd anytime the output of the logic gate is supposed to be 1. Similarly, the PDN connects the output to Vss anytime the output is supposed to be 0.
The PUN and PDN networks are constructed in a mutually exclusive manner such that one and only one of the networks is conducting in steady state.
The Static CMOS gates have rail-to-rail swing , no static power dissipation. The speed of the static CMOS circuit depends on the transistor sizing and the various parasitics that are involved with it. The problem with this type of implementation is that for N fan-in gate 2N number of transistors are required, ie, more area required to implement logic. This has an impact on the capacitance and thus the speed of the gate.
2. Dynamic CMOS
Dynamic CMOS circuits rely on the temporary storage of signal values on the capacitance of high-impedance circuit nodes. These circuits also have no static power dissipation and uses a sequence of precharge and conditional evaluation phases with the addition of a clock input.
The main advantages of the Dynamic CMOS logic are increased speed and reduced implementation area. Fewer devices are used to implement a given logic, this reduces the overall load capacitance and thus increases the speed.