Comparator offset cancellation at which resolution?

[rivendu]

comparator offset cancellation

Hi,

Can you tell me, at which comparator resolution it is necessary to use an offset cancellation technique. I want to build a flash adc and i do not think that latched comparators can be used for resolutions starting at 4bit. Is it right?
Is it possible to build a 10bit flash adc with offset cancellated latched comparators with preamplifiers?
Can you recommend the multistage offset cancellation technique presented by razavi?

Thanks

 

[crystalballs]

comparator multistage

Hi,

Can you tell me, at which comparator resolution it is necessary to use an offset cancellation technique.

Thanks

n-bit FlashADC must resolve 1/2^n Volts so you need to have a comparator offset less than 1/2^n Volts. In my opinion you should use the offset cancellation technique from a resolution greater than about 8 bits because without it the comparator offset is at least about 4mV (1/2^8). Smaller offset values are hard to be obtained also with a good layout.

CBs.

 

[mickey_melomane]

comparator offset resoultion

Offset cancellations may be done, using the auto zero method, at every stage of the preamplifier. U may refer to the paper by Naveen Verma, for a latch offset compensation...

 

[mahgoub]

first you calculate the offset using a statistical model
then compare it with your adc lsb(step) if it is 10lsb this means the first ten steps the adc output is zero

 

[rivendu]

i think it is important to know the offset of the comparator with its input common mode range. when developing a flash adc, the icmr of the comparator is the maximum voltage area to be approximated by the adc. if the area (delta of vrefp and vrefn) should be equal to the icmr of the comparator, then the max. offset of the comparator lets conclude the max. bit resolution of the flash adc.
do you agree?

 

[wonbef]

according to your requirements of precission