Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Common Mode Level at Output

Status
Not open for further replies.

suhas_shiv

Full Member level 2
Joined
Nov 30, 2005
Messages
136
Helped
11
Reputation
22
Reaction score
4
Trophy points
1,298
Activity points
2,461
This question has been asked once but I am putting this up again, for I didn't quite get a good answer.
Usually the output common mode level is to be kept at the avg of the positive and negative power supplies. Any reasons why we do that?

Appreciate the reponse.

Thanks
 

eecs4ever

Full Member level 3
Joined
Jan 31, 2006
Messages
179
Helped
28
Reputation
56
Reaction score
10
Trophy points
1,298
Location
Analog Environment
Activity points
2,852
If you place the output level too high, or too low. Clipping will occur when the input
signal is large enough. See picture below. If you place the output level too high, you will more likely run into Vdd, and cause your signal to clip. If you place your output level too low, you will more likely hit ground, causing your signal to clip.

But if you place the output level near the middle. Your out put will have the most room to swing. (the bottom case in the drawing)

This is important if you want your amplifier to be linear. This is especially important
if the amplitude of the signal carries information that you need later.

For example, in AM modulation, the information is encoded in the amplitude. So clipping will cause you to lose your data !

Or the signals going to your speaker. If they are clipped before they reach your speakers, your music will not sound very good.

Clipping is a very ugly distortion.

Hope that helps.
 

suria3

Full Member level 5
Joined
Mar 5, 2004
Messages
304
Helped
17
Reputation
34
Reaction score
5
Trophy points
1,298
Activity points
3,042
To have a symmetrical signal output (avoiding signal/data degradation)
 

montage2000

Member level 1
Joined
Jan 7, 2006
Messages
39
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,584
not the average, but the midpoint of the effective output voltage
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top