Apr 29, 2020 #1 P PGPPG Newbie Joined Apr 23, 2020 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 48 Hello, Is it allowed to use comma(',') in 'always' statement? I accidently used comma(',') instead of 'or' in 'always' statement when desining a clock generator in verilog HDL. like this: always @(negedge RST, posedge CLK) begin ~ end I'd like to ask whether using comma works differently from using 'or', and if it is different, how it is different. Actually I didn't notice any unexpected operation during verificaiton of its operation. Thank you. PG
Hello, Is it allowed to use comma(',') in 'always' statement? I accidently used comma(',') instead of 'or' in 'always' statement when desining a clock generator in verilog HDL. like this: always @(negedge RST, posedge CLK) begin ~ end I'd like to ask whether using comma works differently from using 'or', and if it is different, how it is different. Actually I didn't notice any unexpected operation during verificaiton of its operation. Thank you. PG
Apr 29, 2020 #2 pancho_hideboo Advanced Member level 5 Joined Oct 21, 2006 Messages 2,847 Helped 767 Reputation 1,536 Reaction score 733 Trophy points 1,393 Location Real Homeless Activity points 17,490 PGPPG said: I'd like to ask whether using comma works differently from using 'or' Click to expand... Same. However synthesized results might be different. ‘,’ is recommended, since inside ‘()’ is Sensitivity List. Last edited: Apr 29, 2020
PGPPG said: I'd like to ask whether using comma works differently from using 'or' Click to expand... Same. However synthesized results might be different. ‘,’ is recommended, since inside ‘()’ is Sensitivity List.
Apr 29, 2020 #3 P PGPPG Newbie Joined Apr 23, 2020 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 48 Thank you very much for your reply. Waiting my question to be uploaded, I found a reference for your comment in IEEE standard of system Verilog 2017. - IEEE Standard for SystemVerilog-Univied Hardware Design, Specification, and Verification Language, p.218, 2017 Thank you so much. PG
Thank you very much for your reply. Waiting my question to be uploaded, I found a reference for your comment in IEEE standard of system Verilog 2017. - IEEE Standard for SystemVerilog-Univied Hardware Design, Specification, and Verification Language, p.218, 2017 Thank you so much. PG
Apr 29, 2020 #4 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,421 Helped 14,749 Reputation 29,780 Reaction score 14,101 Trophy points 1,393 Location Bochum, Germany Activity points 298,103 Right, also discussed in this recent thread https://www.edaboard.com/showthread.php?388945-The-difference-between-operator-and-keyword-or Respectively, synthesized results should be never different.
Right, also discussed in this recent thread https://www.edaboard.com/showthread.php?388945-The-difference-between-operator-and-keyword-or Respectively, synthesized results should be never different.