hello,
here is an interesting scenario..
i`ve main design coded in vhdl...
processor bfm in systemverilog...
and a micron memory model in verilog...
Using modelsim Altera 6.6d, how to verify the main design.
what are steps to be followed during instantiation....
In general, using VHDL, Verilog and SystemVerilog together in a design requires no special steps. The ASIC i am working on has hundreds of blocks wriiten in all three HDLs and I have not had to do anything differently than I would if all modules were written in the same HDL.
Specifically, though, the question of whether or not your particular version of Modelsim can use mixed HDLs would be answered by the manual or on Altera's website.
thank u r.b. for ur reply...
nw my question is while compiling the files vhdl uses vcom command and verilog/systemvg use vlog. then compiling all the modules do i need to seperatethe module like
1.vcom (specifying vhdl files/modules)
2.vlog (specifying verilog/smvlg files/modules)?
thank u r.b. for ur reply...
nw my question is while compiling the files vhdl uses vcom command and verilog/systemvg use vlog. then compiling all the modules do i need to seperatethe module like
1.vcom (specifying vhdl files/modules)
2.vlog (specifying verilog/smvlg files/modules)?
Like rb I have a design which uses all three languages and I use a .do file to compile the design and run the simulation. The .do file has a set of vcom lines to compile the VHDL and then a vlog line to compile a file that contains all the design files in a single `include file.