combining group of signals in verilog to form like structure

[guru hegde]

Hi,

I have a group of incoming signals with different bit width belonging
to single transaction. I have to store all these inside FIFO or buffer
and forward all these to different block.I am coding in verilog. Is
there any way to do this without creating individual queue for each
signal.
Do verilog has something similar to structure in C so my problem can
be solved??

 

[FvM]

Verilog has a concatenation operation.

assign abc = {a,b,c};

 

[ads-ee]

If you want something similar to a C structure, systemverilog has interfaces, which Vivado supposedly has support for http://www.xilinx.com/support/answers/51837.html. Interfaces are supported by synthesis, but I'm pretty sure that the Vivado simulator doesn't support interfaces.

To connect to the buffer/FIFO you'll still have to use concatenation like FvM suggested as none of the IP generated by Xilinx/Altera use interfaces.

 

[guru hegde]

Verilog has a concatenation operation.

assign abc = {a,b,c};

yeah..it didn't occur to me..:grin:thanks a lot.

 

[dave_59]

You can use a struct in SystemVerilog, just like in C; No need to use an interface, and most synthesis tools already support structs.

If you stick with the Verilog approach, just use {a,b,c} on the LHS or RHS of any assigment, no need to create a separate signal abc.

 

[ads-ee]

Oops, I was thinking of struct, but thought that was the VHDL version (which is actually record), so instead I suggested an interface.

Trouble is the synthesis tools support both (including Xilinx), but as I have access to either an ancient perpetual Modelsim license that supports up to Verilog 2001, Xilinx ISE's ISIM, or Vivado's XSIM I'm kind of stuck with not getting to use any of the System Verilog keywords nor added Verilog stuff. Complaining about simulation support for the latest version of the SV standard (even the non-SV stuff) falls on deaf ears a Xilinx (so I've given up complaining). It's really nice that Xilinx started supporting some of the synthesizable SV keywords, but what's the point in using them if you can run a simulation with them in the HDL.