`include "defines.v"
module fifo_top(w_clk,
r_clk,
rst_n,
w_en,
r_en,
w_data,
r_data,
w_full,
r_empty);
input w_clk;
input r_clk;
input rst_n;
input w_en;
input r_en;
input [`DATA-1:0] w_data;
output [`DATA-1:0] r_data;
output w_full;
output r_empty;
wire [`DATA-1:0] r_data;
wire w_full;
wire r_empty;
wire w_rst;
wire r_rst;
wire [`ADDR-1:0] w_addr;
wire [`ADDR-1:0] r_addr;
wire [`ADDR-1:0] r_addr_gray;
wire [`ADDR-1:0] r_addr_gray_sync;
wire [`ADDR-1:0] r_addr_bin_sync;
wire r_almost_empty_sync;
wire r_almost_empty;
rst_sync w_rst_sync(.clk(w_clk),
.rst_n(rst_n),
.rst_sync(w_rst));
rst_sync r_rst_sync(.clk(r_clk),
.rst_n(rst_n),
.rst_sync(r_rst));
d_sync #(`ADDR) r_addr_sync(.clk(w_clk),
.rst_n(w_rst),
.input_data(r_addr_gray),
.output_data(r_addr_gray_sync));
/*bin_to_gray_converter b_t_g_conv(.bin_data(r_addr),
.gray_data(r_addr_gray));*/ //Modified for Lint
gray_to_bin_converter g_t_b_conv(.gray_data(r_addr_gray_sync),
.bin_data(r_addr_bin_sync));
addr_ctrl wr_rd_ctrl(.w_clk(w_clk),
.r_clk(r_clk),
.w_rst(w_rst),
.r_rst(r_rst),
.w_en(w_en),
.r_en(r_en),
.w_addr(w_addr),
.r_addr(r_addr),
.r_addr_gray(r_addr_gray),
.w_full(w_full),
.r_empty(r_almost_empty_sync));
fifo_controller fifo_ctrl(.clk(w_clk),
.rst_n(w_rst),
.w_addr(w_addr),
.r_addr_sync(r_addr_bin_sync),
.w_full(w_full),
.r_empty(r_empty),
.r_almost_empty(r_almost_empty));
d_sync_1 #(1) almost_empty_sync(.clk(r_clk),
.rst_n(r_rst),
.input_data(r_almost_empty),
.output_data(r_almost_empty_sync));
rfdp128b66m1p10 fifo_ram(
.QA(r_data),
.AA(r_addr[`ADDR-2:0]),
.CLKA(r_clk),
.CENA(r_en),
.AB(w_addr[`ADDR-2:0]),
.DB(w_data),
.CLKB(w_clk),
.CENB(w_en)
);
endmodule
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this is an example. just use this model. if you still have doubts, feel free to ask.