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coding vga port vhdl

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vhdl34

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im trying to display a red box on a 640 by 480 screen however nothing is
displayed on my vga screen im using nexys 3 and these were the port used
clk v10 ns-n6 vs -p7 red1 -u7 green2 - p8 blue2 -r7 here under is my
code which i made thanks i appriate any help
Code:
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_misc.all; 
use IEEE.std_logic_unsigned.all; 

entity vga is
  port(clk :in std_logic;
      hs : out std_logic;
      vs : out std_logic;
      red1 : out std_logic;
      green2 : out std_logic;
     
blue2: out std_logic
     
      );
            end vga;

Architecture vga_arch of vga is
 
  begin 
       
   
   process(CLK) 
           
         
      
      variable v :std_logic:= '0';
      variable h : std_logic := '1' ;
      variable red :std_logic:= '0';
      variable green :std_logic:= '0';
      variable blue :std_logic:= '0';
       variable x : std_logic_vector(9 downto 0) := "0000000000"  ;
       variable y  : std_logic_vector(9 downto 0) := "0000000000"  ;
      
       
     begin

              
if (CLK'EVENT and CLK = '1') then
 
      if(h = '1') then 
        x := x+ "0000000001" ;
        if(x = "1010000001") then
          h:= '0';
          v := '1';
          x := "0000000000";
        end if;
    elsif(v = '1') then
    y := y + "0000000001";
     V:='0';
     h:='1';
      end if;
      if(y = "0111100001") then 
        y := "0000000000";
      end if;
      hs <= h;
      vs<= v;
      red1 <='1';
      blue2 <='0';
      green2 <='0';
      
       end if;
    end process;
    end vga_arch;
 

the red output is always '1', did you intend to do this?
and have you testbenched the design.
 

yes to have all red pixel
 

im going to use 25 mhz
 

yes i need however to code the timings
 

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