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| behavioral file:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity DCT_beh is
port (
Clk : in std_logic;
Start : in std_logic;
Din : in INTEGER;
Done : out std_logic;
Dout : out INTEGER
);
end DCT_beh;
architecture behavioral of DCT_beh is
begin
process
type RF is array ( 0 to 7, 0 to 7 ) of INTEGER;
variable i, j, k : INTEGER;
variable InBlock : RF;
variable COSBlock : RF;
variable TempBlock : RF;
variable OutBlock : RF;
variable A, B, P, Sum : INTEGER;
begin
COSBlock := (
( 125, 122, 115, 103, 88, 69, 47, 24 ),
( 125, 103, 47, -24, -88, -122, -115, -69 ),
( 125, 69, -47, -122, -88, 24, 115, 103 ),
( 125, 24, -115, -69, 88, 103, -47, -122 ),
( 125, -24, -115, 69, 88, -103, -47, 122 ),
( 125, -69, -47, 122, -88, -24, 115, -103 ),
( 125, -103, 47, 24, -88, 122, -115, 69 ),
( 125, -122, 115, -103, 88, -69, 47, -24 )
);
--Starting
wait until Start = '1';
Done <= '0';
--Read Input Data
for i in 0 to 7 loop
for j in 0 to 7 loop
wait until Clk = '1' and clk'event;
InBlock(i,j) := Din;
end loop;
end loop;
--TempBlock = COSBLOCK * InBlock
for i in 0 to 7 loop
for j in 0 to 7 loop
Sum := 0;
for k in 0 to 7 loop
A := COSBlock( i, k );
B := InBlock( k, j );
P := A * B;
Sum := Sum + P;
if( k = 7 ) then
TempBlock( i, j ) := Sum;
end if;
end loop;
end loop;
end loop;
--Finishing
wait until Clk = '1' and Clk'event;
Done <= '1';
--Output Data
for i in 0 to 7 loop
for j in 0 to 7 loop
wait until Clk = '1' and Clk'event;
Done <= '0';
Dout <= tempblock(i,j);
end loop;
end loop;
end process;
end behaviorall;
testbench file:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY lab4b_tb IS
END lab4b_tb;
ARCHITECTURE behavior OF lab4b_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DCT_beh
PORT(
Clk : IN std_logic;
Start : IN std_logic;
Din : IN INTEGER;
Done : OUT std_logic;
Dout : OUT INTEGER
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Start : std_logic := '0';
signal Din : INTEGER;
--Outputs
signal Done : std_logic;
signal Dout : INTEGER;
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DCT_beh PORT MAP (
Clk => Clk,
Start => Start,
Din => Din,
Done => Done,
Dout => Dout
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable i, j : INTEGER;
variable cnt : INTEGER;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
start <= '1';
wait for clk_period;
start <= '0';
for cnt in 0 to 63 loop
wait until clk = '1' and clk'event;
din <= cnt;
end loop;
--wait for 100 ns;
--start <= '1';
--wait for clk_period;
--start <= '0';
--for i in 0 to 63 loop
-- wait for clk_period;
--if (i < 24) then
--din <= 255;
--elsif (i > 40) then
--din <= 255;
--else
--din <= 0;
--end if;
--end loop;
wait;
end process;
END; |