//DUT
`define value 9 //counter increments only after (9 + 1) clocks
module clock_gen(
input clk_in,
input rst,
output reg [`value-1:0] enable,
output reg [3:0] count
);
always@(posedge clk_in )
begin
if (rst) begin
count <= 4'd0;
enable <= 'd0; end
else
enable <= enable == `value ? 'd0 : enable + 'b01 ;
if(enable == `value)
count <= count + 1'b1;
end
endmodule
//testbench
`define value 9
module tb_clkgen;
// Inputs
reg clk_in;
reg rst;
// Outputs
wire [`value-1:0] enable;
wire [3:0] count;
// Instantiate the Unit Under Test (UUT)
clock_gen uut (
.clk_in(clk_in),
.rst(rst),
.enable(enable),
.count(count)
);
initial begin
// Initialize Inputs
clk_in = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#120;
rst = 0;
// Add stimulus here
end
initial clk_in = 1;
always #10 clk_in =~clk_in;
endmodule