Compare the current consumption and dc levels between schematic and extract (I suppose you are using OA views, nor spf netlist - correct me if my assumption is wrong).
Generate device only extraction and compare the netlists (using for example tkdiff). Check whether mosfet are netlisted with the same parameters (I don't remember whether C35 pdk provides any LDE).
Simulate 4 cases - schematic, extract no parasitic, c only and RC.
If you are using Assura tool (especially version 4.1) to perform LVS and you will see discrepancy in DC operating points, it can be possible that layout is not matched with schematic even with LVS passes by Assura.