anas171
Newbie level 4
Hi all,
I want to design an NMOS varactor in Cadence. where the source and drain of NMOS are shorted together like the attached figure. And the gate is controlled by another voltage. I have all the required parameters of this S/D gate NMOS varactor.
I want to know how do I plot the Cv vs Vgb for this MOS varactor with different (W/L) values like the attached figure. It will be very helpful if anyone can point out the steps serially how to simulate this MOS varactor in UMC 130nm process with Cadence.
I want to design an NMOS varactor in Cadence. where the source and drain of NMOS are shorted together like the attached figure. And the gate is controlled by another voltage. I have all the required parameters of this S/D gate NMOS varactor.
I want to know how do I plot the Cv vs Vgb for this MOS varactor with different (W/L) values like the attached figure. It will be very helpful if anyone can point out the steps serially how to simulate this MOS varactor in UMC 130nm process with Cadence.