Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

CMOS Noise Spectrum Analysis

Status
Not open for further replies.

Nurahmad

Junior Member level 1
Junior Member level 1
Joined
Apr 10, 2013
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Kuala Lumpur
Visit site
Activity points
1,452
Hi,

I want to simulate NMOS and PMOS noise behavior in 130nm technology with Mentor Graphics tool, parameters as below:

Vds=0.7V
Id=185uA
W/L=100/0.4 um
in order to get Id=185uA, Vgs has to be set around 0.36V. I put a AC voltage signal with offset 0.36V, magnitude default is 20mV.

The problem is, when I simulate AC noise behavior, my noise spectrum should be the ONOISE curve or the INOISE curve? (Should I take the drain net noise spectrum curve as my noise behavior of CMOS?)

noise.jpgonoise.jpginoise.jpg

From the images, the Onoise curve from drain net, while the Inoise from gate net.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top