bb12mpc
Newbie level 5
Dear all,
I am doing to a multi-vdd SoC design, there is a high-to-low level shifter available in the process. What I understood on high-to-low shifter is to aviod over-stressing from high-v output to low-v input (pls correct me if I am wrong!).
When I look at the circuit, the high-to-low level shifter is just two inverters inside. Below is the breakdown of this high-to-low level shifter.
A -> inverter (vdd: low-v, pmos: 0.37/0.13, nmos 0.3/0.13) -> inverter (vdd:low-v, pmos:0.85/0.13, nmos: 0.69/0.13) -> Y
Could someone explain how it works and why it can avoid over-stressing?
Many thanks,
Mark
I am doing to a multi-vdd SoC design, there is a high-to-low level shifter available in the process. What I understood on high-to-low shifter is to aviod over-stressing from high-v output to low-v input (pls correct me if I am wrong!).
When I look at the circuit, the high-to-low level shifter is just two inverters inside. Below is the breakdown of this high-to-low level shifter.
A -> inverter (vdd: low-v, pmos: 0.37/0.13, nmos 0.3/0.13) -> inverter (vdd:low-v, pmos:0.85/0.13, nmos: 0.69/0.13) -> Y
Could someone explain how it works and why it can avoid over-stressing?
Many thanks,
Mark