CMOS high-to-low level shifter: how it works?

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Dear all,

I am doing to a multi-vdd SoC design, there is a high-to-low level shifter available in the process. What I understood on high-to-low shifter is to aviod over-stressing from high-v output to low-v input (pls correct me if I am wrong!).

When I look at the circuit, the high-to-low level shifter is just two inverters inside. Below is the breakdown of this high-to-low level shifter.

A -> inverter (vdd: low-v, pmos: 0.37/0.13, nmos 0.3/0.13) -> inverter (vdd:low-v, pmos:0.85/0.13, nmos: 0.69/0.13) -> Y

Could someone explain how it works and why it can avoid over-stressing?

Many thanks,
Mark
 

To avoid the "over-stress", the transistors in the first inverter should be of thick oxide. For example if you want a 3.3V->1.2V level shifter, then the first inverter MUST have 3.3 V transistors. If it has 1.2 V these will be destroyed.
 

Dear maxwellequ,

Thanks for the prompte response. But what I saw from the schmatic of my high-to-low level shifter, the first and second inverters' VDDs are both connecting to the low-v supply.

So, is it wrong on the ciruit? Or the different transistor sizes do the trick?

Thanks,
Mark

maxwellequ said:
To avoid the "over-stress", the transistors in the first inverter should be of thick oxide. For example if you want a 3.3V->1.2V level shifter, then the first inverter MUST have 3.3 V transistors. If it has 1.2 V these will be destroyed.
Click to expand...
 

OK, let me rephrase... Both inverters must be connected to the low-vdd supply, but the transistors of the first inverter MUST be of thick oxide, to avoid burning the transistors. Is is now clear ? Or what you don't understand is how the circuit operates ?
 

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