cmos dimension for operating voltage

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mona123

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Hi, If I use larger channel length device (say 1um) in a 90nm CMOS process, will my maxing safe operating voltage at drain and gate, scale linearly or will it be still be 1V given by foundry for 90nm gate length CMOS? Thanks.
 

Expect to see a big initial change but run into plain oxide
reliability - voltage asymptote before you get to 1um.
1um was 5V logic back in the day. Your short channel Vds
is probably driven by other things but there's always that
one not far behind it, all engineered and traded off.
 
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