cmos diff pair mismatch

[dsula]

Hi,
I have an NMOS diff-pair that exhibits a certain offset. This offset is dependent on the input common mode. I have a hard time explaining this effect. Anybody knows? How can I avoid this? I don't care much about the offset of the diff pair, but I care about the offset not to change across a large common mode input range.

Or to give you some numbers. (The diff pair is used in a unity gain single ended miller op-amp)
I bias the inputs to 2V and I measure 5mV at the output.
I short the inputs to 3V and I measure 8mV at the output.

Thank you all for any thought on this.
ds

 

[rfsystem]

That's simple:

The offset of a NMOS pair depend on matching of the main physical parameters. There are

1. Threshold voltage mismatch
2. Mobility mismatch
3. Substrate effect mismatch

The common mode voltage dependence of the input related offset of the NMOS diffpair is only related to the mismatch if the substrate effect. The threshold voltage of the NMOS change with the source to bulk voltage. If the factor have a mismatch also the the effective threshold voltage change with common mode voltage.

You can use isolated NMOS, if avaible, by connecting the common source to isolated bulk.

 

[dsula]

thanks a lot, that's what I suspected.
I will switch to PMOS pairs and tie the NWELL to the tail.

 

[jimway]

thanks a lot, that's what I suspected.
I will switch to PMOS pairs and tie the NWELL to the tail.

Switching to PMOS pairs and tie the NWELL to the tail won't improve the mismatch alot. The mismatch of diff pair is a function of the overdrive voltage. Try to increase the W/L to lower the Vov, and that might help.

 

[rfsystem]

jimway,

the question was why the offset because of mismatches change with common mode voltage. Please read the post!

 

[jimway]

Hi,
I have an NMOS diff-pair that exhibits a certain offset. This offset is dependent on the input common mode. I have a hard time explaining this effect. Anybody knows? How can I avoid this? I don't care much about the offset of the diff pair, but I care about the offset not to change across a large common mode input range.

Or to give you some numbers. (The diff pair is used in a unity gain single ended miller op-amp)
I bias the inputs to 2V and I measure 5mV at the output.
I short the inputs to 3V and I measure 8mV at the output.

Thank you all for any thought on this.
ds

The opamp is not fully differential. And according to the amplitude of the mismatch, the systematic mismatch dominated. So the more effecient way is to increase the input common mode range or increase the voltage gain.