Cmos Design Problem Help

[Brdav19]

I have a design problem that is similar to the design problem in my text book and I was wondering how to get started.

Using the 0.25 μm CMOS technology introduced in Chapter 2, design a static CMOS
inverter that meets the following requirements:

a. Matched pull-up and pull-down times (i.e., tpHL = tpLH).

b. tp = 5 nsec (+/- 0.1 nsec).

The load capacitance connected at the output is equal to 4 pF. Notice that this capacitance
is substantially larger than the intrinsic capacitances of the gate. Determine the W and L
of the transistors. To reduce the parasitics, use minimal lengths (L = 0.25 μm) for all
transistors. Verify and optimize the design using ADS after proposing a first design using
manual computations. Compute also the energy consumed per transition.

I know you have to treat the transistors as a resistor, but after that I'm lost.

 

[saurabhr8here]

Delay is CV/I, so if you know all these values and current equation of a MOSFET (I), figuring out delay should be easy, right? Since this is an inverter, you want to make sure that the current through the NMOS and PMOS are the same, so essentially, size the PMOS so that you get the same current. There are better approximations given in textbooks, but this approach is a very simple first order estimate.