CMOS comparator for sigma delta ADC

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sandhaajith

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cmos comparator

Can anyone suggest how to design a comparator for sigma delta ADC
 

cmos comparator circuit design

hi sandhaajith,

the offset and hysteresis requirements of the comparator in sigma-delta modulator is relaxed and the high-speed is required, so it can be designed with a preamplifier followed by a latch with reset.

see this paper:
“A High-Speed CMOS Comparator with 8-b Resolution,” IEEE J. of Sold-State Circuits Feb.1992, pp.208-211.
 

comparator sigma delta

really?
I think comparator nonlinearity is a key issue in sigma delta design, because it can not be attenuated
by loop, is itn't
 

cmos sigma-delta modulator of adc

What does it mean by "comparator nonlinearity"?
Please explain more...
Thanks
 

design cmos comparator

i understand that comparator non linearities are
offset
metastability
memory effect
kickback noise
overdrive recovery
to name a few

Added after 1 minutes:

can u tell me how to select ucox for a mosfet?
 

cmos comparator resolution

jcpu said:
What does it mean by "comparator nonlinearity"?
Please explain more...
Thanks
Click to expand...
Linear circuits are circuits whose input signals are linearly related to the circuit's output. e.g.
X -> Y
aX -> aY

I dont think comparators are linear in the first place. For example,
X -> Y
aX -> Y
 

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