CMOs 180nm capacitance per unit area -

[yippie]

Hello,

I'm designing a charge (split) scaling DAC, with 8 bit resolution. I am working between 0.8V and 1V and have 1mm² of silicon area @ 180nm process available.

How do I calculate the size of my capacitors required? I have no idea how big they should be. Can someone please explain to me how one calculates the values. As it's a split array my largest capacitor needs to be 8x the smallest one.

Thanks
Thomas



N.B: I found this
https://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/tsmc-018/t92y_mm_non_epi_thk_mtl-params.txt

 

[dick_freebird]

A MOS capacitor is going to have lousy linearity. So
that leaves you with a MIM, POP, MOM type capacitor
and all of these are pretty "decoupled" from FEOL
lithographic capability - your 180nm choice has not
much to do with it other than that MIM caps will scale
oxide thickness somewhat following the transistor
BVdss plus margin - how much, comes down to foundry
particulars.

The other thing about your caps is, they need the
switches and sense-amp loads to be trivial w.r.t.
the explicit LSB capacitor value. So you might want
to get a viable switch and charge amplifier figured
out first, and then find a LSB cap value that holds
net charge "well enough" when you look at the
assembly as a whole, by an optimization loop
(diminishing returns vs performance goals).

 

[erikl]

How do I calculate the size of my capacitors required? I have no idea how big they should be. Can someone please explain to me how one calculates the values.

Cf. this posting.