CML based XOR gate simulation problem for high speed in Cadence (IBM 130nm)

[gangnam_style]

Hi,
For the design of a CML based XOR gate, at low frequency it works fine.
As I increase the frequency ~1GHz, the o/p has a delayed rise time. What parameters do I need to change to get the accurate waveforms?

W/L ratios in the attachment Schematic

Waveform here
Q is the output.

IBM 130nm technology.
Tail current 10uA.

 

[dick_freebird]

1.2K pullup load and 10uA tail current means a 120mV signal
swing, stop-to-stop. That is not much. And 1.2K times a
tenth of a picofarad would account for your 100pS-range
risetime. If you want to drive any wireload at all, you will
want to lower the load resistor value and bump up the tail
current. You also ought to look at optimizing the device
W particularly, which (net Cds*N) is your unloaded risetime
driving factor pretty much.