CLOCK_50 was determined to be clock but was found without an associated clock assign.

Hello,

I am having an issue in combining two clocks signals in one project. I am using DE2 Altera board. I am also using Nios processor. So, basically I am trying to merge to independently working projects into one and build my thing on it. I have one clock signal 50MHz for one project and I have another 27MHz signal for another project. I ported mapped all modules correctly to one project and everything went fine.

But then I am not getting what I wanted when programming my FPGA. I am getting the following warnings:

CLOCK_50 was determined to be clock but was found without an associated clock assignment.
PLL1|altpll_component|PLL|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of :20.00
PLL2|altpll_component|PLL|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of :20.00

Someone have an idea on this?

Thanks!

You should learn a bit about TimeQuest and timing constraints.

As FvM states learn about timing constraints...

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_timequest_cookbook.pdf