when you guys talk about clock latency and clock uncertainty, I would prefer these 2 values bind with a certain design phase, say, if you are in the early phase of the design, just start synthesis, no P&R yet, then there 2 values are only estimated one, you can put clock jitter + clock skew target for the uncertainty and put a estimated clock latency. however, as the work continues, after CTS, you can get more precise value for your clock latency (propagated) one, you can choose to re-synthesis your design with this value, as for the uncertainty, it must be reduced or modified, because after CTS, the tool propagated the clock and knows exactly the skew numbers, of course SI and OCV also taken care by the tool, so you must modify your sdc to adjust your clock uncertainty, if not, you can end up with a big design, because hold fixing put lots of delay buffers to the design since your uncertainty value is too big.