Feb 7, 2014 #1 E eda_rattle Newbie Joined Jul 8, 2011 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,308 Hi All, What are the reasons for keeping the max_transition at clock nets higher than data nets ? Only due to Xtalk ? Or there are other reasons also. For eg, in postcts stage if you have : set_max_transition 1.0 -clock_path [get_clocks X_CLK] set_max_transition 1.2 [get_designs *] Thanks & Regards, eda_rattle
Hi All, What are the reasons for keeping the max_transition at clock nets higher than data nets ? Only due to Xtalk ? Or there are other reasons also. For eg, in postcts stage if you have : set_max_transition 1.0 -clock_path [get_clocks X_CLK] set_max_transition 1.2 [get_designs *] Thanks & Regards, eda_rattle
Feb 10, 2014 #2 R rca Advanced Member level 5 Joined May 20, 2010 Messages 1,527 Helped 355 Reputation 710 Reaction score 336 Trophy points 1,363 Location Marin Activity points 8,773 no reason. better clock tree?
Mar 14, 2014 #3 E eda_rattle Newbie Joined Jul 8, 2011 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,308 Then why clock is kept at higher transition & not data ?