The 7 series FPGAs use BRAMs that have a maximum width of 64bits (72 if you use parity). Therefore whether or not you use Coregen to generate a x1024 memory, or you infer one in your code, or you generate 16 x64 memories, you will physically end up with 16 memories. Moreover, since each BRAM is a maximum of 32 kbits (36k if you use parity), all your BRAMs would be 512 bits deep. So if you need a x1024 deeper than that, you would need 32 or more BRAMs.
Having said all that, Coregen would take care of the timing issues for you when it generates the memory.
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