dll_fpga
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Very simple.
There is no problem in using the clock signal as select input for multiplexer.
Mux operation depends on the clock value at that instant of time. This is also known as Time Division Multiplexing. (TDM)
eg: Consider a 2to1 Mux. When clock signal (Select S) is '0' the the first input(a) comes out of the MUX and when it goes to '1' the second input(b) comes out of the MUX. You can have the time division as you like i.e having clock input '0' for t1 sec and '1' for t2 sec. t1 and t2 can be of your wish.
All the best.
Hi,
There will definitely be a problem, if you are using a continuously switching signal as a select.
You need to have a clock gating check performed at these points, and if you are getting a violation then you need to fix them before proceeding.
The clock gating check can be ignored only in the case when the select signal of the mux is static during the operation, else there would be undue clipping of the signal.
Is the warning related to this or someting else ?
Please do not proceed on theretical concepts only, go through all warnings and errors...
thanks,
Shobhit
Can you post the exact warning ?
Can you post the exact warning ?
Can you post the exact warning ?
The question can't be answered without considering the purpose of the mux output signal. Instead of raising general questions, you should analyze your design's timing. in detail.in my case the clock signal is used for selecting data inputs...
So is it necessary to fix the clock gating violations?
The question can't be answered without considering the purpose of the mux output signal. Instead of raising general questions, you should analyze your design's timing. in detail.
A mux driven by a clock can be e.g. found in DDR output buffers, but it's of little use for internal logic, I think.
hi shobit,
the clock signal is used as the select of a mux for selecting 2 data input signals to the mux..
when it is 0...input 1 is selected ...when it is 1 input 0 is selected
if the inputs of the mux were clocks rather than data...clock gating checks are to be done as u said...
but in my case the clock signal is used for selecting data inputs...
So is it necessary to fix the clock gating violations?
This select clock is always toggling...
please explain ...
Yes, but this scenario doesn't seem to serve a reasonable purpose.You may run into issues if clk appears in the combinatorial path for a register that is clocked off of clk or a derived version. In such cases, the input to the FF will change near the same time as the FF's clock signal.
STA become critical
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