Hi,
I have bought a Virtex-7 board. The board has a 100MHz Silicon Labs programmable clock (570FBC000642DG). The problem is that I can't use this clock. I used an IBUFGDS in this manner:
Does the V7 board have external differential termination on the clock? If no then you'll need to enable the on-die termination. It's something like DIFF_TERM=TRUE. Look up the exact UCF syntax.
You can also check if the OE pin of the SiLab part is high to make sure it's output is enabled.
Which tool you are using?
Is it Xilinx or Vivado?
I think it should be vivado, if its vivado, you should use the *.xdc file instead of *.ucf file.
If you are using the *.xdc file, then the constraints are different,
NET constraints are using in *.ucf file, but in *.xdc file you should use