Clock Problem VHDL Spartan 3E (RS 232)

[come512l]

My Vhdl program seems to work when I remove the external clock, but when I add the clock to the RS 232 Reciever Code, It doesn't work anymore in the testbench.

I'm trying to make a UART application, PC to Spartan 3E, my PC (hyperterminal is set to 9600 baud rate) so I have to supply the clock RX DCE from the spartan 3 to match with the baud rate. (I have only done this on testbench on Xilinx) :roll:

My vhdl program is this: I have to send a word to a PC via hyper terminal and sent it to Spartan 3E via RS 232, then there will be an output on the LED depending on the set of WOrds that I sent. E.g BLINK --- output in LED is blinking


Clock code for RX (RS 232)

entity ClockGen is
    Port ( CLK_in : in  STD_LOGIC;
           CLK_out : out  STD_LOGIC);
end ClockGen;

architecture Behavioral of ClockGen is

begin
	process (CLK_in)
	variable count : integer := 0;
	variable clk : STD_LoGIC := '0';
	begin
		if falling_edge(CLK_in) then
			count := count + 1;
			if count = 2600 then
				clk := not clk;
				count := 0;
			end if;
		end if;
		CLK_out <= clk;
	end process;

end Behavioral;

Here is what it looks like on the Top Module (Removing the Clock on THe RS232 and the CU makes the program seems to work)

 

[vinodkumar]

query is not clear....put in proper way....

 

[TrickyDicky]

Basic answer: dont create a clock in logic. Use clock enables instead.

 

[come512l]

I've added more info