Hi,
I´d use the returning clock (from CCD) directely as DFF clock.
This is a clean solution. (As long as you select the correct clock edge)
Then use additional DFF to synchronize the data from first DFF to your FPGA system clock.
--> Both clocks are synchronous, but phase shifted (delayed). Here - depending on delay time - you again need to select the correct clock edge.
This avoids the use of PLL.
(synchrounous serial SDR data transfer)
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But for sure the PLL solution should be "clean", too.
Klaus