Clock Period over-constraining vs Setup Uncertainty

[ivlsi]

Hi All,

Why is Setup Uncertainty needed? Why not just over- constrain the Clock Period?

E.g., instead of setting the Setup Uncertainty to 20%, why not to define the Clock Period smaller in 20% than its original one?

Hold violations are not handled during Logic Synthesis. So, is Clock Uncertainty for Hold redundant?

Thank you!

 

[rca]

both are possible, you just need to be consistant over your flow.

 

[ivlsi]

Should uncertainty be defined separately for MIN and MAX delays or the definitions are just for HOLD and SETUP?
I mean I need to define MIN and MAX uncertainty for HOLD and MIN and MAX uncertainty for SETUP or just a single uncertainty for HOLD and a single for SETUP?