aok_fine
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Hi everyone,
In fractional N plls the divider value is dithered by a sigma delta modulator. I need to know is this sigma delta modulator is clocked by reference clock or the divider output? And Why? Also, if we had higher frequency clocks can they be used instead?
Thanks in advance
In fractional N plls the divider value is dithered by a sigma delta modulator. I need to know is this sigma delta modulator is clocked by reference clock or the divider output? And Why? Also, if we had higher frequency clocks can they be used instead?
Thanks in advance
