I have two input clocks, CLKA and CLKB.
They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a constant.
So, how should I define the clocks of this circuit?
I have two input clocks, CLKA and CLKB.
They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a constant.
So, how should I define the clocks of this circuit?
I have two input clocks, CLKA and CLKB.
They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a constant.
So, how should I define the clocks of this circuit?
I know it is very old thread, But I need some help on this as you tested on DC.
I am using the same code which you mentioned for my design. I am not able to perform STA properly. I want to do power analysis for each clock and at the same time want to check how many registers clocked during case_analysis, so I am using the set_case_analysis but it is not working, means if I set select pin as 1 or 0 in both the case both the clocks are going to all registers. Have you experienced this issues, do I need to set any other constraints please let me know.
Anybody who knows anything about this, then please give some suggestion.