Apr 8, 2008 #1 C caosl Advanced Member level 4 Joined Mar 26, 2006 Messages 114 Helped 17 Reputation 34 Reaction score 4 Trophy points 1,298 Activity points 1,969 dac clock jitter hi, all How to model the clock jitter in current steering DAC, and how to simulate this effect ( in behavior model or in circuit level simulation)?
dac clock jitter hi, all How to model the clock jitter in current steering DAC, and how to simulate this effect ( in behavior model or in circuit level simulation)?
Apr 8, 2008 #2 A alard Member level 4 Joined Dec 2, 2004 Messages 70 Helped 4 Reputation 8 Reaction score 1 Trophy points 1,288 Activity points 551 jitter in a current steering dac Usually I will add a disturbing signal at around 30GHz