Jul 9, 2008 #1 Y yanivh Newbie level 3 Joined Feb 26, 2008 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,299 I have 10MHz clock signal and i need to generate it complementray signal by 0.5µm cmos design. Multiplication of the clock and its complementray must be as close to zero for all time to minimize glitch. What designs i can refer to?
I have 10MHz clock signal and i need to generate it complementray signal by 0.5µm cmos design. Multiplication of the clock and its complementray must be as close to zero for all time to minimize glitch. What designs i can refer to?