clock gating- problems

[sagar_eda]

hi
i'm using RTL level clock gating in my design for reducing power consumption.

i'm taking everything ideal(setup time=0, hold time=0)

after inserting clock gating and after synthesis, i'm getting large hold time violations.

help me how to solve this
thank you

 

[haykp]

My belief is that you are inserting the gating logic by UPF, please confirm. If so, then I believe you have mixed in upf language.
Otherwise if you doing by verilog, then may be the tool doesn't understand whats is going there so you need to give sdc constraints to tool, to allow the tool understand where is the false where is the real path.

 

[sagar_eda]

i am not using UPF. i am using Synopsys Design Compiler to insert RTL level clock gating using "insert clock_gating" command

---------- Post added at 09:57 ---------- Previous post was at 09:56 ----------

hold violations at the input of FFs

 

[lostinxlation]

Sorry to say this but your question is like from a 5 year old kid. If someone asks you "my car has a problem. Please let me know how to fix it", can you give him a solution ?

 

[srihari_adem]

why r u bothering about hold violations at synthesis stage ?
Clock gating hold violations can fixed like other hold violations during physical design phase.
Techniques can used to fix hold violations are clock skewing/buffering in data path near to endpoint.

 

[sagar_eda]

so you are telling no need to consider hold violations at synthesis level.

my doubt is these violations are very large, even then?

 

[srihari_adem]

yes..no need to bother about hold violations because clock is ideal during synthesis (no CTS). All hold violations will get fixed in post route database.

 

[lostinxlation]

If you have a huge hold violations after synthesis, there is something wrong, either logic or constraints or library. You have to fix it.

 

[srihari_adem]

might be you can try "set_clock_gating_check" to fix hold violations at synthesis stage for specified clock gating cells.

 

[lostinxlation]

I think the first step is finding out what caused the hold viols. If it's a simple hold viol, ignore it till the backend, but if it's caused by other reasons, most likely required to fix them.

The problem is the OP didn't even provide the details and there is no way to help.

 

[yx.yang]

First, Using ICG cell(or Latch) do clock gate will have better timing than NAND, OR gate.