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clock-gating on Virtex Pro II FPGA

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Dec 2, 2012
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Hello everybody!
I'm working with a Virtex II Pro (specifically, I'm working with a NetFPGA ).
I'm aiming to stop the clock in certain modules when there is no traffic, to obtain less energy consumption. I'm doing this by using a buffer that's present on the board, to enable the clock only when necessary to such modules.

The problem is, doing it this way I won't meet timing constraints. I even tried to make the board work with 62.5MHz instead of the default 125MHz, but it's still not enough. Note that in this configuration all the board works with the 62.5MHz clock: some modules will work with a "gated" version of that clock and some with the "regular" one (I need to keep some modules working all the time because otherwise i wouldn't be able to tell if there are packets arriving at all and to turn on again the rest of the system).

I read a way to make it work would be to have registers clocked with negative edge inbetween those working with the "regular" clock and those with the gated clock, but also this doesn't help.

Any suggestions?
Thank you very much in advance

(ps: I'm programming in Verilog)
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I'm not sure why you're not meeting timing constraints, unless the external buffer you're using has excessive propagation delay. If the gated clock and 'ungated' clock both go through identical buffers, then any skew between the two clocks should be minimal. Do you mean timing constraints within the FPGA or for the whole board?

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