clock gating - Latch Vs Negative Edge Flipflop

[analog_fever]

I have seen many sources recommending the use of a negative level sensitive latch, and an AND gate for clock gating. The enable signal is fed to a latch that uses ~clock as the activating signal. The latched enable, and the clock signal are AND gated to get the gated clock.

I am wondering why can't we use a negedge flipflop instead? When I draw the waveforms I do not see any difference in the clock gating function. Also for timing, and scan the negedge flop seems better. The only advantage I see with the latch is that it uses less # of gates than the flop.

Can some expert point out if there are any other advantages of using the latch?

I searched the forum and found that this question has been asked already, but has not been answered properly. Hence I am asking again.

 

[yx.yang]

Yes, they are function the same. But:
1: latch usually smaller than DFF --- gate count save
2: latch will have 1T time for clock gating setup check, while DFF will just give 0.5T time for setup --- better timing

 

[analog_fever]

// 2: latch will have 1T time for clock gating setup check, while DFF will just give 0.5T time for setup --- better timing //

Thank you. Can you elaborate on this?

 

[yx.yang]

Hi, friend: It's hard to descrip without a figure.
I think you may using the following ways to figure it out:
1): DO you have DC, then you can write a design with AND and Latch_AND as the clock gating design. Then ask DC synthesis the design and report the timing.
2): To better understand why the timing will be calculated, you can google some papers talking about this matter.

 

[dftrtl]

We gain 1/2 Cycle time extra in timing using the LATCH over negedge FLOP when LATCH is opened.
The other gain is we can use the negedge FLOP output as OUTPUT of module, where as latch path would be combo path.