Oct 8, 2013 #1 S sharath666 Advanced Member level 2 Joined Apr 4, 2011 Messages 552 Helped 126 Reputation 252 Reaction score 124 Trophy points 1,323 Location India Activity points 3,830 Hi all, Could you tell me why do some people avoid clock gating for synchronizers while enabling it for the rest of the design? Regards, Sharath
Hi all, Could you tell me why do some people avoid clock gating for synchronizers while enabling it for the rest of the design? Regards, Sharath
Oct 8, 2013 #2 Vengateswaran Member level 5 Joined Sep 13, 2013 Messages 85 Helped 14 Reputation 30 Reaction score 13 Trophy points 8 Location Coimbatore, India Activity points 427 It is mainly due to possibility of occurrence of metastable state..
Oct 8, 2013 #3 S sharath666 Advanced Member level 2 Joined Apr 4, 2011 Messages 552 Helped 126 Reputation 252 Reaction score 124 Trophy points 1,323 Location India Activity points 3,830 Could you kindly explain why is the possibility of metastability occurring more here?
Oct 8, 2013 #4 Vengateswaran Member level 5 Joined Sep 13, 2013 Messages 85 Helped 14 Reputation 30 Reaction score 13 Trophy points 8 Location Coimbatore, India Activity points 427 The changing clock level may cause this state which can lead to data corruption.. In all the cases, handshaking will be followed and so there is no possibility or less probability of data corruption...
The changing clock level may cause this state which can lead to data corruption.. In all the cases, handshaking will be followed and so there is no possibility or less probability of data corruption...
Oct 8, 2013 #5 S sharath666 Advanced Member level 2 Joined Apr 4, 2011 Messages 552 Helped 126 Reputation 252 Reaction score 124 Trophy points 1,323 Location India Activity points 3,830 Thank You...
Oct 9, 2013 #6 E er.akhilkumar Full Member level 2 Joined Feb 1, 2011 Messages 120 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,298 Location Noida Activity points 2,418 Please mark the threads as solved if you think you are satisfied with the answer.