In my design we have a clock mux whose select line is driven by positive edge trigerred flip-flop. I know that its difficult to meet hold check in such scenario because hold check will be done from launch edge to next half cycle edge.
In that case if I do an MCP of 2 on setup and MCP 1 on hold from the flip-flop which drives the select line how will the timing arc be affected? Will hold check be more relaxed then?
is the clock select expected to change during runtime or is it set before any meaningful operation begins? if the latter case, a false path could be enough.