# Clock Frequency Division with varying frequency

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#### nishanthp68

##### Newbie level 6
I have a main clock . I should divide the clock according to the number present in a 32 bit register which keeps on varying at regular intervals . Can some one suggest me how this can be done ?? The duty cycle of the new clock should be 50 % or anywhere close.
I tried in the following manner , even though the code works theoretically It will not synthesize.

Code:
module divclk(division_register,clk,mcclk);

input [31:0] division_register;
input clk;
output mcclk;
reg mcclk;
real divrreal;
real count = 0;
initial begin
mcclk = 0;
end

always @(posedge clk)
begin
divrreal = \$bitstoreal (division_register);
if (count/2 >= divrreal)
begin
count = 0;
mcclk = ~ mcclk;
end
else
begin
count = count + 0.01;
end
end
endmodule

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