@barry, you are discussing frequency and the possibility you might need a 3 stage synchronizer.
The paper the OP has quoted is discussing the width of the slow clock data being transferred to the faster clock domain to reliably have at least 1 of the clock edges in the faster domain seeing a valid setup/hold of the signal in the slower clock domain.
The 1.5x cycle width is to guarantee that any signal from the slow clock domain is stable for a least 1.5 cycles of the faster clock domain (assuming the setup+hold isn't >=0.5 of the faster clock domain)