Feb 19, 2019 #1 N Nanda_DFT Newbie level 5 Joined Feb 19, 2019 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 40 How to avoid bit getting launched in 1 clock domain and getting captured in another clock domain? needed theoretical concept
How to avoid bit getting launched in 1 clock domain and getting captured in another clock domain? needed theoretical concept
Feb 19, 2019 #2 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,549 Helped 397 Reputation 794 Reaction score 464 Trophy points 1,363 Activity points 14,767 I don't understand the question. If the design has multiple clock domains, the transition from one to the other is natural and intended. During test, the entire IC could be run using a shared test clock, thus eliminating the domain crossing issue.
I don't understand the question. If the design has multiple clock domains, the transition from one to the other is natural and intended. During test, the entire IC could be run using a shared test clock, thus eliminating the domain crossing issue.
Feb 20, 2019 #3 N Nanda_DFT Newbie level 5 Joined Feb 19, 2019 Messages 8 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 40 Thank you for providing me the hint.. :thumbsup: